1. Field of the Invention
This invention relates to a duty cycle correction circuit of a delay locked loop in a Rambus dynamic random access memory (DRAM), and more particularly to a duty cycle correction circuit in a delay locked loop for reducing the refresh time by compulsorily correcting the capacitance of a storage capacitor lost in transition from a power save mode to a normal mode to a predetermined value.
2. Description of the Related Art
In general, a Rambus DRAM is a packet driving type memory device which transfer data and control signals with a packet. A Rambus controller controls Plural Rambus DRAMs through a Rambus channel and plural Rambus DRAMs are connected to a Rambus channel. A Rambus interface is constituted in the respective Rambus DRAM, respectively so as to transfer data through the Rambus channel between them. Because the plural Rambus DRAMs coupled to the Rambus channel is controlled by one controller, the respective Rambus DRAMs have different phase differences so as to recognize the data and the control signals from the controller at the same time. That is, in case of the Rambus DRAM which is far separated from the controller, it makes the data to be processed fast and in case of the Rambus DRAM which is near the controller, it makes the data to be processed slowly.
Generally, the Rambus DRAM includes a normal mode and a power save mode, wherein the power save mode includes a nap mode and a power down mode. FIG. 1 shows a circuit of a Rambus DRAM having a power save mode in the prior art. The Rambus DRAM having the power save mode includes a packet controller 200 for analyzing a control packet signal Ctrl_PKT from an external channel to generate a control signal Cntrl for controlling a power mode operation and an operation code signal op_code for determining an operation mode.
The Rambus DRAM includes a power mode controller 300 which generates a nap mode signal Nap and a power down mode signal PDN and a self refresh enable signal Self_Refresh_en by the control signal Cntrl from the packet controller 200. The Rambus DRAM includes a delay locked loop circuit 400 which receives the power down mode signal PDN and the nap mode signal Nap and an external clock signal CLK_in to generate an internal clock signal CLK_out and a memory core 100 having a refresh counter controlled by the self refresh enable signal Self_refresh_en.
The packet controller 200 receives the packet control signal Ctrl_PKT from an external channel outside the Rambus DRAM and generates the control signal Cntrl and the operation code signal op_code. The control signal Cntrl is a signal for controlling whether the Rambus DRAM operates with the power save mode, or not and the operation code signal op_code is a signal of 2 bits for determining the respective operation modes. For example, in case of the operation code signal op_code of 2 bits, the op_code of xe2x80x9c00xe2x80x9d forbids the Rambus DRAM to be changed into the power save mode, and the op_code of xe2x80x9c01xe2x80x9d changes it to a power down mode, and the op_code of xe2x80x9c10xe2x80x9d changes it to a nap mode Nap and the op_code of xe2x80x9c11xe2x80x9d changes it to a doze mode.
The power mode controller 300 receives the operation code signal op_code and the control signal Cntrl from the packet controller 200 to generate the self refresh enable signal Self_Refresh_en to the memory core 100 and the nap mode signals Nap and the power down mode signals PDN to the delay locked loop circuit 400. The self refresh enable signal Self_fresh_en controls the refresh counter built in the memory core 100 to perform the self refresh operation. The nap mode signal Nap and the power down mode signal PDN control the delay locked loop (DLL) circuit 400 to operate in accordance with the power state.
The delay locked loop circuit 400 receives the clock signal CLK_in received from the exterior of the system and generates the internal clock signal CLK_out required interior the system with synchronization to the phase of the external clock signal CLK_in.
The construction and operation of the delay locked loop circuit 400 will be described with reference to FIG. 2. The delay locked loop circuit 400 includes a controller 410, a bias generator 420, a duty cycle correction circuit 430, a phase detector and mixer 440, a clock amplifying part 450 and a clock buffer 460. The controller 410 controls the bias generator 420, the duty cycle correction circuit 430 and the phase detector and mixer 440, the clock amplifying part 450 and the clock buffer 460 by the nap mode signal Nap and the power down mode signal PDN from the power mode controller in FIG. 1.
The duty cycle correction circuit 430 generates a control signal for controlling a clock pulse width of high or low state to the clock amplifying part 450 by a mode signal from the controller 410 and a bias signal from the bias generator 420. The clock buffer 460 generates the internal clock signal CLK_OUT having the same phase difference as the external clock signal CLK_IN to an interior of the system.
The phase detector and mixer 440 receives the external clock signal CLK_IN and the final clock signal CLK_OUT from the clock buffer 460 and compares the phases of the clock signals to control the clock amplifying part 450 and the clock buffer 460 to coincide the phase difference between the clock signals.
The clock amplifying part 450 amplifies the clock signal from the phase detector and mixer 440 and provides the amplified signal to the clock buffer 460. The bias generator 420 provides the bias to the duty cycle correction circuit 430 and the clock buffer 460 by the mode signal from the controller 410.
FIG. 3 shows the duty cycle correction circuit of the delay locked loop circuit in the prior art. The prior duty cycle correction circuit 430 includes a differential amplifying stage 432 which differential-amplifies two clock signals clki and clkib as input signals to generate output signals through nodes Nd6 and Nd7, when the bias voltage Vbiasn from the bias generator 420 has a high level and the mode signal napb which indicates not the nap mode Nap but the power save mode has a high level.
The prior duty cycle correction circuit 430 further includes a signal transfer switch stage 434 for providing the output signals Nd6 and Nd7 from the differential amplifying stage 432 to first and second output terminals dcc and dccb by control signals capon and caponb and a storage capacitor stage 436 for storing the output signals dcc and dccb of the first and second output signals.
First, when the bias voltage Vbiasn from the bias generator 420 has a high level and the mode signal napb indicating the power save mode has a high level, the NMOS transistors N3-N6, N9, N10, N15 and N16 and the PMOS transistors P1-P3 and P5-P7 are turned on to be ready to the differential amplifying stage 432 to operate. If the input signals clki and clkib are provided to gates of the NMOS transistors N1 and N2, the differential amplifying stage 432 generates the differential-amplified output signals though the node Nd6 and Nd7. If the bias voltage Vbiasn is a high level and the mode signal napb is a high level, when the clock signal clki is a high level and the clock signal clkib is a low level, the output signal of the node Nd6 becomes a low level and the output signal of the node Nd7 becomes a high level.
The signal transfer switching stage 434 includes a transfer gate including a PMOS transistor P9 and a NMOS transistor N19 for transferring the output signal Nd6 of the differential amplifying stage 432 as the output signal dccb by the control signals capon and caponb; a transfer gate including a PMOS transistor P12 and a NMOS transistor N20 for transferring the output signal Nd7 of the differential amplifying stage 432 as the output signal dcc by the control signals capon and caponb.
The signal transfer switching means 434 includes a NMOS transistor N21 for a capacitor connected between the control signal caponb and the output signal dccb; a PMOS transistor P10 for a capacitor connected between the output signal dccb and the control signal capon; and a NMOS transistor N22 for a capacitor connected between the control signal caponb and the output signal dcc and a PMOS transistor P11 for a capacitor connected between the output signal dcc and the control signal capon.
The signal transfer switching stage 434 provides the output signals Nd6 and Nd7 of the differential amplifying stage 432 as the output signals dccb and dcc when the control signal capon is a high level and the control signal caponb is a low level.
The storage capacitor stage 436 includes NMOS transistors N23 and N24 for capacitors connected between the output signal dccb and the ground voltage Vss and between the output signal dcc and the ground voltage Vss, respectively.
FIG. 4A shows a generator of the mode signal napb used in FIG. 3. The napb mode signal generator includes inverters INV1-IV3 connected in series for receiving the nap mode signal Nap to generate the mode signal napb. The nap mode signal Nap has the opposite phase to the mode signal napb. In the nap mode, the Nap signal is a high state and the napb signal is a low state. In the power save mode, the Nap signal is a low state and the napb signal is a high state.
FIG. 4B is a generator of the control signals capon and caponb used in FIG. 3. The control signal generator includes inverters INV4-INV7 connected in series for receiving the DLLhold signal to generate the control signal caponb and an inverter INV8 for receiving output signal of the inverter INV7 to generate the control signal capon. In the power save mode, the DLLhold signal is a high state and the control signals capon and the caponb are low and high states, respectively.
However, the prior duty cycle correction circuit 430 has a disadvantage as follows. In the power save mode, after the lapse of a long time, the data stored in the capacitor of the memory cell is lost owing to the leakage. It requires a setting time of several hundred of nanosecond ns to several microsecond xcexcs in order to set the lost data to the capacitor in the memory cell. Accordingly, in the power save mode of the Rambus DRAM which is the nap mode and the power down mode, in case of the nap mode which should use the data stored in the capacitor as it is, the exit time is about 100 ns. But the tolerance time is very short at several xcexcs and the power consumption of 4 mA is caused. In case of the power down mode, there is no limit of the tolerance time and the power consumption of 1 mA is caused. But the exit time is very long at several xcexcs.
It is an object of the present invention to provide a duty cycle correction circuit of a delay locked loop to solve the problem that the refresh time for refreshing data to a storage capacitor in a power save mode is very short in a nap mode and the refresh time is very long in a power down mode having no time limit.
It is an object of the present invention to provide a duty cycle correction circuit of a delay locked loop having a power save function with high speed operation and no time limit by compulsorily correcting the capacitance of a storage capacitor lost in transition from a power save mode to a normal mode to a predetermined value.
According to an aspect of the present invention, there is provided to a duty cycle correction circuit of a delay locked loop of Rambus DRAM having a normal mode and a power save mode including a nap mode and a power down mode, comprising: a signal input unit receiving a first control signal, an enable signal, a first input signal and a first input bar signal, and outputting signals differentially amplifying the first input signal and the first input bar signal by a first potential difference to a first node and a second node when the first control signal indicates a nap mode in a state that the enable signal is active, and outputting signals differentially amplifying the first input signal and the first input bar signal by a second potential difference to a first node and a second node when the first control signal indicates the normal mode in a state that the enable signal is active; a signal output unit including a first storage unit connected between the first node and ground voltage and storing the signals of the first node, a second storage unit connected between the second node and ground voltage and storing the signals of the second node, a first voltage supplying unit transmitting ground voltage to the first node when a second signal indicates the power down mode, a second voltage supplying unit transmitting ground voltage to the second node when the second control signal indicates the power down mode, a first transmission gate unit transmitting ground voltage a signal of the first node to a first output terminal when the second control signal indicates a normal mode, a second transmission gate unit transmitting a signal of the second node to a second output terminal when the second control signal indicates a normal mode, a third storage unit connected between the first output terminal and ground voltage and storing signals of the first output terminal, a fourth storage unit connected between the second output terminal and ground voltage and storing signals of the second output terminal, a third voltage supplying unit discharging the first output terminal to ground voltage when the second control signal indicates the power down mode, a fourth voltage supplying unit discharging the second output terminal to ground voltage when the second control signal indicates the power down mode; and a signal transfer unit connected between the signal input unit and the signal output unit, the signal transfer unit connecting the signal input unit and the signal output unit when the third control signal indicates the normal mode, and the signal transfer unit blocking the connection between the signal input unit and the signal output unit when the third control signal indicates the power save mode.
In the duty cycle correction circuit, each of the first to fourth storing units is comprised of a capacitor which is a NMOS transistor.
In the duty cycle correction circuit, the first power voltage is a power supply voltage of Vdd and the second power voltage is a ground voltage of Vss.
In the duty cycle correction circuit, each of the first and second voltage supply units is comprised of a PMOS transistor and each of the third and fourth voltage supply units is comprised of a NMOS transistor.
In the duty cycle correction circuit, the signal transfer unit is comprised of a transmission gate. The capacitor is comprised of MOS transistors and preferably a PMOS transistor and a NMOS transistor.